1. Field of the Invention
The present invention relates to a method of manufacturing a multilayer wiring substrate having a laminate structure in which a plurality of resin insulation layers made primarily of the same resin insulation material and a plurality of conductor layers are laminated alternately in multilayer arrangement, and not having a so-called substrate core in a final product, the substrate core carrying build-up layers successively formed on opposite surfaces thereof.
2. Description of Related Art
In association with recent increasing tendency toward higher operation speed and higher functionality of semiconductor integrated circuit devices (IC chips) used as, for example, microprocessors of computers, the number of terminals increases, and the pitch between the terminals tends to become narrower. Generally, a large number of terminals are densely arrayed on the bottom surface of an IC chip and flip-chip-bonded to terminals provided on a motherboard. However, since the terminals of the IC chip differ greatly in pitch from those of the motherboard, difficulty is encountered in bonding the IC chip directly onto the motherboard. Thus, according to an ordinarily employed method, a semiconductor package configured such that the IC chip is mounted on an IC chip mounting wiring substrate is fabricated, and the semiconductor package is mounted on the motherboard.
The IC chip mounting wiring substrate which partially constitutes such a semiconductor package is practicalized in the form of a multilayer substrate configured such that a build-up layer is formed on the front and back surfaces of a substrate core. The substrate core used in the multilayer wiring substrate is, for example, a resin substrate (glass epoxy substrate or the like) formed by impregnating reinforcement fiber with resin. Through utilization of rigidity of the substrate core, resin insulation layers and conductor layers are laminated alternately on the front and back surfaces of the substrate core, thereby forming respective build-up layers. In the multilayer wiring substrate, the substrate core serves as a reinforcement and is formed very thick as compared with the build-up layers. Also, the substrate core has conductor lines (specifically, through-hole conductors, etc.) extending therethrough for electrical communication between the build-up layers formed on the front and back surfaces.
In recent years, in association with implementation of high operation speeds of semiconductor integrated circuit devices, signal frequencies to be used have become those of a high frequency band. In this case, the conductor lines which extend through the substrate core serve as sources of high inductance, leading to the transmission loss of high-frequency signals and the occurrence of circuitry malfunction and thus hindering implementation of high operation speed. In order to solve this problem, a multilayer wiring substrate having no substrate core is proposed. This multilayer wiring substrate does not use a substrate core, which is relatively thick, thereby reducing the overall wiring length. Thus, the transmission loss of high-frequency signals is lowered, whereby a semiconductor integrated circuit device can be operated at high speed.
In this method of manufacturing a multilayer wiring substrate, a metal foil is disposed on a support substrate (base material), and a plurality of conductor layers and a plurality of resin insulation layers are laminated on the metal foil to thereby form a build-up layer. Subsequently, the metal foil is separated from the support substrate so as to obtain a structure in which the build-up layer is formed on the metal foil. After that, the metal foil is removed through etching so as to expose the surface of the outermost layer of the build-up layer (the surface of the resin insulation layer and the surfaces of a plurality of connection terminals), whereby the multilayer wiring substrate is manufactured. Furthermore, there has been put to practical use a multilayer wiring substrate in which a solder resist layer is formed on the outermost layer of the build-up layer. Notably, the solder resist layer has openings for exposing the surfaces of the connection terminals. The solder resist layer is made primarily of a hardened resin insulation material that is photocurable, and formed on the outermost layer of the build-up layer after the structure is separated from the support substrate. In this case, since the solder resist layer is formed in a state in which the support substrate has been removed (in a coreless state); i.e., in a state in which the structure is composed of the build-up layer only, the structure does not have sufficient strength at that time. Thus, forming the solder resist layer having a uniform thickness becomes difficult, which may result in a decrease in production yield.
In order to solve such a problem, there may be employed a manufacturing method in which a solder resist layer is formed on a support substrate, and a build-up layer is formed on the solder resist layer. Patent Documents 1 and 2 disclose such a manufacturing method.